Linghao Song — Researcher Analysis Report
Analysis Mode: fast | Analysis Time: 2026-03-16T00:46:11
Rating: Early Researcher (22.0/100)
Basic Metrics
| Metric | Value |
|---|---|
| Institution | Unknown |
| h-index | 2 |
| Total Citations | 33 |
| Recent 5 Years Citations | 22 |
| Total Papers | 3 |
| Top Conference Papers | 0 |
| Publication Period | 2020 - 2023 |
| Semantic Scholar | 2150597993 |
Research Trajectory
Linghao Song is a researcher focusing on computer architecture, whose research trajectory centers around in/near-memory computing. In 2017, he won the Best Paper award with GraphR, a ReRAM graph processing accelerator, establishing his early reputation in non-volatile memory computing. During 2020–2022, he reached his peak period, systematically constructing a complete research ecosystem around sparse linear algebra acceleration (SpMV, SpMM, conjugate gradient solvers) and the FPGA high-level synthesis framework (TAPA). In 2023, he appeared at the computer architecture top conference ISCA with NDSEARCH, transferring near-data processing paradigms to vector databases and LLM retrieval-enhanced generation scenarios, completing a key transition from traditional HPC to AI systems.
A key feature of his growth trajectory is the dual progression of ’tools + applications’: the TAPA/RapidStream-IR series provides FPGA programming infrastructure, while the Serpens/Sextans/NDSEARCH series are high-impact applications driven by this infrastructure. This self-developed toolchain strategy gives his research strong reproducibility and community influence. Notably, two cosmology/neutrino papers (related to the Seesaw mechanism) published in 2024 are completely separate from other research directions, likely belonging to researchers with the same name but different individuals, and are not included in this trajectory analysis.
Breakthrough Work
1. GraphR: Accelerating Graph Processing Using ReRAM (2017)
Description: Proposed the first ReRAM resistive memory-based graph processing accelerator, directly mapping the graph adjacency matrix onto the ReRAM cross-array, using analog circuits to perform large-scale parallel matrix-vector multiplications, thereby bypassing the memory bandwidth bottleneck in traditional von Neumann architecture and achieving extremely low-energy graph computing.
Why it couldn’t be done before: ReRAM devices were not yet mature in technology before 2015, with high variability between devices making precise control of conductivity difficult. A critical insight missing was: previous researchers treated ReRAM as a substitute for digital storage, while GraphR systematically demonstrated the core compatibility that ‘graph computing tolerates high precision, and sparse matrices naturally suit parallel simulation domains’, making simulated errors acceptable.
Impact: Initiated the research direction of ‘ReRAM as a computing substrate’. The Best Paper award made it one of the landmark works in near-memory computing, directly triggering numerous subsequent ReRAM accelerator studies; the methodology (mapping sparse matrices to analog arrays) was widely cited and extended.
2. Refloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers (2020)
Description: Addressed the most critical engineering challenge in ReRAM simulation computing: floating-point support. Proposed decomposing floating-point operations into forms that can be executed at low cost in ReRAM and applied to iterative linear solvers (core operators in scientific computing), published in the supercomputing top conference SC.
Why it couldn’t be done before: Floating-point operations require high precision (IEEE 754 single-precision needs 23-bit mantissa), while ReRAM simulation computing inherently has noise. Previously, it was generally believed that ‘ReRAM is only suitable for low-precision integer/fixed-point operations’. A key insight missing was: iterative solvers in scientific computing have self-converging properties, allowing intermediate steps to use mixed precision; Refloat found a controllable balance between precision error and convergence speed, representing a cognitive breakthrough rather than mere engineering improvement.
Impact: Expanded the applicability of ReRAM acceleration from graphs/neural networks to scientific computing, opening up new research space for HPC+ReRAM; 11 citations in SC papers indicate a robust performance.
3. TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design (2022)
Description: Proposed the TAPA end-to-end compilation framework, allowing users to describe computations with C++ task-parallel dataflow programs and automatically compile into high-frequency FPGA accelerators. The key innovation is simultaneous co-optimization of high-level synthesis (HLS) and physical layout, solving the persistent problem of frequency collapse in large-scale FPGA designs.
Why it couldn’t be done before: Mainstream tools such as Xilinx Vitis HLS treat HLS and physical implementation as separate stages, resulting in significantly reduced frequency after layout and routing. A core insight missing was: task-parallel granularity naturally aligns with the SLR (Super Logic Region) physical partitions of FPGAs; recognizing physical constraints during the HLS stage enables high productivity and performance simultaneously. This requires deep understanding of both FPGA architecture and HLS internal mechanisms, reflecting cross-layer abstraction capabilities.
Impact: Became an important foundational tool for academic FPGA accelerator research; subsequent TAPA-CS further expanded to distributed multi-FPGA scenarios; reduced the development barrier for high-performance FPGA accelerators.
4. NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing (2023)
Description: Proposed a near-data processing acceleration scheme for graph-traversal-based approximate nearest neighbor search in vector databases, published at the computer architecture top conference ISCA, directly targeting the underlying indexing core of LLM retrieval-enhanced generation (RAG).
Why it couldn’t be done before: Graph-traversal algorithms for ANNS were mainly regarded as software/algorithmic problems before 2022; the explosive growth of LLM+RAG in 2022–2023 made ANNS a critical load in data centers, generating strong motivation for hardware acceleration. At the computing level, there was insufficient empirical data to prove that ANNS is a memory bandwidth bottleneck rather than a computational one; NDSEARCH provided key evidence through profiling, making the near-data processing scheme compelling.
Impact: 22 citations indicate it is the most cited work so far, coinciding with the LLM infrastructure boom; shifted the attention of the architecture community toward vector databases, driving numerous subsequent ANNS accelerator studies.
Research Directions
- Near-memory/cache computing and hardware accelerator design (ReRAM, HBM, NDP)
- Sparse linear algebra and graph computing acceleration (SpMV, SpMM, graph traversal)
- FPGA high-level synthesis and programming frameworks (TAPA, RapidStream)
- System acceleration for AI/LLM infrastructure (ANNS, vector databases, RAG)
Methodological Evolution
Early (2017–2019) focused on simulation computing paradigms, using ReRAM physical properties to perform matrix operations; the core methodology was trade-off analysis of ‘precision for energy efficiency’. From 2020–2021, shifted to digital sparse accelerator design; the methodology upgraded to ‘dataflow analysis + memory access pattern modeling’, focusing on solving load imbalance and random memory access issues in sparse computing. The release of the Pyxis dataset also reflected emphasis on system evaluation methodologies. In 2022, introduced the ‘cross-layer co-optimization’ methodology; TAPA spans programming model, HLS compiler, and physical design, marking a shift from single accelerator to a complete toolchain. In 2023, methodology evolved toward ‘workload-driven architecture design’; NDSEARCH starts from real LLM application scenarios to analyze performance bottlenecks and then drives hardware architecture decisions, reflecting a mature system research paradigm anchored by application needs.
Overall, the methodological evolution path is: simulation near-memory computing → digital sparse acceleration → compiler and hardware co-optimization → architecture driven by AI applications. Throughout, continuous attention is paid to memory bandwidth bottlenecks, with solutions evolving from simulation computing to HBM utilization and then to near-data processing.
Domain Impact
Linghao Song’s contributions in computer architecture are reflected in two dimensions: first, directional contributions. GraphR (2017 Best Paper) and NDSEARCH (ISCA 2023) sent guiding research signals at two distinct time points—ReRAM graph acceleration and vector database acceleration—respectively. The former inspired a generation of ReRAM accelerator work, while the latter coincided with the LLM infrastructure boom and led to widespread follow-up research. Second, infrastructure contributions: the TAPA framework was used as an open-source tool, reducing the entry barrier for FPGA accelerator research and having a multiplier effect. From citation distribution, 22 citations of NDSEARCH were concentrated within just two years after publication in 2023, indicating strong recent influence in the intersection of AI systems and architecture, closely aligning with current LLM infrastructure research hotspots.
Highly Cited Papers (Top 20)| # | Year | Citation | Title |
|—|——|——|——| | 1 | 2023 | 22 | NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing | | 2 | 2020 | 11 | Refloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers | | 3 | 2017 | 0 | GraphR: Accelerating Graph Processing Using ReRAM | | 4 | 2017 | 0 | Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses | | 5 | 2018 | 0 | DPatch: An Adversarial Patch Attack on Object Detectors | | 6 | 2019 | 0 | Deep Learning for Vertex Reconstruction of Neutrino-Nucleus Interaction Events with Combined Energy and Time Data | | 7 | 2019 | 0 | HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array | | 8 | 2020 | 0 | SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training | | 9 | 2021 | 0 | Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication | | 10 | 2021 | 0 | Pyxis: An Open-Source Performance Dataset of Sparse Accelerators | | 11 | 2021 | 0 | Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication | | 12 | 2022 | 0 | Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver | | 13 | 2022 | 0 | TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design | | 14 | 2023 | 0 | In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search | | 15 | 2023 | 0 | TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs | | 16 | 2024 | 0 | Cosmological Signatures of Neutrino Seesaw Mechanism | | 17 | 2024 | 0 | Cosmological Non-Gaussianity from Neutrino Seesaw Mechanism | | 18 | 2024 | 0 | RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis |